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DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 1 of 35 applications ? low voltage, high density systems with intermediate bus architectures (iba) ? point-of-load regulators for high performance dsp, fpga, asic, and microprocessor applications ? desktops, servers, and portable computing ? broadband, networking, optical, and communications systems benefits ? integrates digital power conversion with intellige nt power management ? eliminates the need for external power management components ? programmable via industry-standard i 2 c communication bus (dpm required) ? reduce the number of discrete parts within a power system. ? reduces board space, system cost, complexity and time to market features ? input voltage range: 8v?14v ? high continuous output current: 5a ? wide digitally programmable output voltage range: 0.7v?5.5v ? single-wire serial communication bus between dpol and digital power manager (dpm) ? programmable dynamic output voltage positioning fo r better load transient response ? overcurrent, overvoltage, undervoltage, and overtemperature protections with programmable thresholds and hiccup or latching modes ? programmable fixed switching frequency: 500khz or 1.0mhz ? programmable switching frequency phasing ? programmable turn-on and turn-off delays ? programmable turn-on and turn-off output voltage slew rates with tracking protection ? in-system loop identification (sysid) through pseudo-random noise injection ? power good signal with programmable threshold and delay ? advance fault management and propagation ? start up into pre-biased load ? real time voltage, current, and temperature measurements, monitoring, and reporting ? industry standard size through-hole single-in-line vertical package: 1.2?x0.26x0.84? ? compatible with conventional pick-and-place equipment ? wide operating temperature range -40c - 85c ? ul 60950-1/csa 22.2 no. 60950-1-07 second edition, iec 60950-1: 2005, and en 60950-1:2006 (pending) description power-one?s DP8105 is an intelligent, fully program mable step-down point-of-load dc-dc converter integ rating digital power conversion and intelligent power mana gement. the dpol is used in conjunction with dm7300 series digital power manager (dpm), and completely elimina tes the need for external components for output vol tage setting, sequencing, tracking, protection, monitori ng, error amplifier compensation and reporting. all performance parameters of the DP8105 are programmable and manag ed through digital power manager via the industry- standard i 2 c communication bus and can be changed by a user at any time during product development and operation. telemetry data is available in real time and can be accessed over the i2c bus.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 2 of 35 reference documents: ? dm7300 digital power manager data sheet ? dm7300 digital power manager programming manual ? power-one i2c gen ii graphical user interface ? dm00056-kit usb to i 2 c adapter kit. user manual 1. ordering information dp 81 05 g ? zz product family: dpwer ? series: intelligent dpol converter output current: 5a rohs compliance: g - rohs compliant for all six substances dash packaging option 1 t100 - 100pcs t&r q1 ? 1pc sample for evaluation only example: DP8105g-t100 : a 100-piece tray of rohs compliant dpol converter s. each dpol converter is labeled DP8105g. 2. absolute maximum ratings stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long- term reliability, and cause permanent damage to the converter. parameter conditions/description min max units inductor or printed circuit board (pcb) temperature input voltage applied -40 125 c input voltage 250ms transient 15 vdc output current (see output current de-rating curves) -4 5 adc 3. environmental and mechanical specifications parameter conditions/description min nom max units ambient temperature range -40 85 c storage temperature (ts) -55 125 c weight 8 grams mtbf calculated per telcordia technologies sr-332 6.24 mhrs peak reflow temperature DP8105g 245 260 c lead plating DP8105g 100% matte tin moisture sensitivity level DP8105g 3 1 packaging option is used only for ordering and not included in the part number printed on the dpol con verter label.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 3 of 35 4. electrical specifications specifications apply at the input voltage from 8v t o 14v, output load from 0 to 5a, ambient temperatur e from -40c to 85c. test conditions include an output fi lter with 2 x 330 f 20m solid electrolytic plus 1 x 22 f x7r ceramic output capacitors, unless otherwise noted. . 4.1 input specifications parameter conditions/description min nom max units input voltage (v in ) 8 14 vdc input current (at no load) v in =14.0v, v out =3.3v 50 madc undervoltage lockout ramping up ramping down 5 7.5 vdc vdc vldo input current current drawn from the external low voltage supply at vldo=8v 50 madc 4.2 output specifications parameter conditions/description min nom max units output voltage range (v out ) 0.7 5.5 vdc output voltage setpoint resolution 2.5mv (1lsb) output voltage setpoint accuracy 2 nd vo loop enabled (0.6% + 5mv) output current (i out ) v in min to v in max -5.5 2 7 adc line regulation v in min to v in max 0.3 %v out load regulation 0 to i out max 0.2 %v out dynamic regulation peak deviation settling time slew rate 1a/ s, 50 -75% load step f sw =500khz to 10% of peak deviation see output load transient section 50 60 mv s output voltage peak-to-peak ripple and noise scope bw=20mhz full load v in =8.0v, v out =0.7v v in =8.0v, v out =2.5v v in =8.0v, v out =5.5v v in =14v, v out =0.7v v in =14v, v out =2.5v v in =14v, v out =5.5v 10 20 40 18 35 50 mv mv mv mv mv mv temperature coefficient v in =12v, i out =0.5i out max 20 ppm/c switching frequency default 500 khz programmable to 500 / 1,000 duty cycle limit default programmable, 1.56% steps 3.125 90.5 100 % % 2 at negative (sink) output current (bus terminator mode) the efficiency of the DP8105 degrades resulti ng in increased internal power dissipation and switching noise. therefore maximum allowable negative current under specific condition s is lower than the current determined from the de-rating curves shown in paragraph.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 4 of 35 4.3 protection specifications parameter conditions/description min nom max units output overcurrent protection type default programmable non-latching, 130ms period latching/non-latching threshold default programmable in 11 steps 36 132 132 % iout % iout threshold accuracy -20 +20 %i ocp.set output overvoltage protection type default programmable non-latching, 130ms period latching/non-latching threshold default programmable in 10% steps 110 130 130 %v o.set %v o.set threshold accuracy measured at v o.set =2.5v -2 2 %v ovp.set delay from instant when threshold is exceeded until the turn-off command is generated 6 s turn off behavior 3 default programmable to emergency off critical off / emergency off output undervoltage protection type default programmable non-latching, 130ms period latching/non-latching threshold default programmable in 5% steps 75 75 90 %v o.set %v o.set threshold accuracy measured at v o.set =2.5v -2 2 %v uvp.set delay from instant when threshold is exceeded until the turn-off command is generated 6 s turn off behavior 3 default programmable to sequenced off sequenced / critical off overtemperature protection type default programmable non-latching, 130ms period latching/non-latching turn off threshold temperature is increasing 120 c turn on threshold temperature is decreasing after the module was shut down by otp 4 110 c threshold accuracy -5 5 c delay from instant when threshold is exceeded until the turn-off command is generated 6 s turn off behavior 3 default programmable to sequenced off sequenced / critical off tracking protection (when enabled) 3 sequenced off: the turn-off follows the turn-off d elay and slew-rate settings; critical off: at turn- off both low and high switches are immediately disabled; catastrophic off: at turn-off the high side switch is disabled and the low side switch is enabled. 4 otp clears when overtemp warning (status register t w bit) turns off.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 5 of 35 type default programmable disabled latching/non-latching, 130ms threshold enabled during output voltage ramping up 250 mvdc threshold accuracy -50 50 mvdc delay from instant when threshold is exceeded until the turn-off command is generated 6 s overtemperature warning threshold always enabled, reported in status register (tw bit) 5 110 c threshold accuracy from nominal set point -5 +5 c hysteresis 1.7 c power good signal (pg pin) logic v out is inside the pg window v out is outside the pg window high low lower threshold default programmable in 5% steps 90 90 95 %v o.set %v o.set upper threshold default programmable in 5% steps 105 110 110 %v o.set threshold accuracy measured at v o.set =2.5v -2 2 %v o.set pg on delay 6 default 0 ms programmable at 0, 10, 50, 150 pg off delay default pg disabled when v out v uv threshold programmable same as pg on delay pg disabled at turn-off command (reset function) 5 temp warning error same sign and proportional with otp error. 6 from instant when threshold is exceeded until statu s of pg signal changes high
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 6 of 35 4.4 feature specifications parameter conditions/description min nom max units interleave interleave (phase shift) default programmable in 22.5 steps 0 0 337.5 degree degree sequencing 7 turn on delay default programmable in 1ms steps 0 0 255 ms ms turn off delay default programmable in 1ms steps 0 0 63 ms ms tracking turn on slew rate default programmable in 8 steps 0.05 0.05 2.0 8 v/ms v/ms turn off slew rate default programmable in 8 steps -0.05 -0.05 -2.0 8 v/ms v/ms optimal voltage positioning load regulation default programmable in 7 steps 0 0 2.45 mv/a mv/a feedback loop compensation proportional (kr) programmable 0.01 2 integral (ti) programmable 1 100 s differential (td) programmable 1 100 s differential roll-off (tv) programmable 1 100 s monitoring voltage monitoring accuracy 12 bit resolution over 0.5?5.5v -0.5 0.5 % current monitoring accuracy 20% i out < i out < i out nom -20 +20 %i out temperature monitoring accuracy junction temperature of dpol controller -5 +5 c remote voltage sense (+vs and ?vs pins) 9 voltage drop compensation between +vs and vout 300 mv voltage drop compensation between -vs and pgnd 100 mv 7 timing based on sd clock and subject to tolerances of sd. 8 achieving fast slew rates under specific line and l oad conditions may require feedback loop adjustment . see rising and falling slew rates.. 9 for remote sense, it is recommended to place a 0.0 1-0.1 f ceramic capacitor between +vs and ?vs pins as clo se to the dpol converter as possible.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 7 of 35 4.5 signal specifications parameter conditions/description min nom max units vdd internal supply voltage 3.15 3.3 3.45 v logic vin max pull up logic max safe input vdd+.5 v sync/data line (sd pin) vil_sd low level input voltage -0.5 0.3 x vdd v vih_sd high level input voltage 0.75 x vdd vdd + 0.5 v vhyst_sd hysteresis of input schmitt trigger 0.25 x vdd 0.45 x vdd v vol low level sink current @ 0.5v 14 60 ma tr_sd maximum allowed rise time 10/90%vdd 300 ns cnode_sd added node capacitance 5 10 pf ipu_sd pull-up current source at vsd=0v 0.3 1.0 ma freq_sd clock frequency of external sd line 475 525 khz tsynq sync pulse duration 22 28 % of clock cycle t0 data=0 pulse duration 72 78 % of clock cycle inputs: addr0?addr4, en, im vil_x low level input voltage -0.5 0.3 x vdd v vih_x high level input voltage 0.7 x vdd vdd+0.5 v vhyst_x hysteresis of input schmitt trigger 0.1 x vdd 0.3 x vdd v rdnl_addr external pull down resistance addrx forced low 10 kohm power good and ok inputs/outputs iup_pg pull-up current source input forced low pg 25 110 a iup_ok pull-up current source input forced low ok 175 725 a vil_x low level input voltage -0.5 0.3 x vdd v vih_x high level input voltage 0.7 x vdd vdd+0.5 v vhyst_x hysteresis of input schmitt trigger 0.1 x vdd 0.3 x vdd v iol low level sink current at 0.5v 4 20 ma current share bus (cs pin) iup_cs pull-up current source at vcs = 0v 0.84 3.1 ma vil_cs low level input voltage -0.5 0.3 x vdd v vih_cs high level input voltage 0.75 x vdd vdd+0.5 v vhyst_cs hysteresis of input schmitt trigger 0.25 x vdd 0.45 x vdd v iol low level sink current at 0.5v 14 60 ma tr_cs maximum allowed rise time 10/90% vdd 100 ns
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 8 of 35 5. pin assignments and descriptions pin name pin number pin type buffer type pin description notes ok 8 i/o pu fault/status condition connect to ok pin of other dpols in the same group and the dpm. sd 9 i/o pu sync/data line connect to sd pin of dpm . pg 6 i/o pu power good addr4 10 i pu dpol address bit 4 tie to gnd for 0 o r leave floating for 1 addr3 5 i pu dpol address bit 3 tie to gnd for 0 or leave floating for 1 addr2 4 i pu dpol address bit 2 tie to gnd for 0 or leave floating for 1 addr1 3 i pu dpol address bit 1 tie to gnd for 0 or leave floating for 1 addr0 2 i pu dpol address bit 0 tie to gnd for 0 or leave floating for 1 vout 1 p output voltage gnd 7 p power ground vin 11 p input voltage legend: i=input, o=output, i/o=input/output, p=powe r, a=analog, pu=internal pull-up
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 9 of 35 6. typical performance characteristics 6.1 thermal de-rating curves ambient temperature [c] 20 30 40 50 60 70 80 90 load current [adc] 0 1 2 3 4 5 6 500 lfm (2.5 m/s) 400 lfm (2.0 m/s) 300 lfm (1.5 m/s) 200 lfm (1.0 m/s) 100 lfm (0.5 m/s) 30 lfm (0.15 m/s) figure 1. available output current vs. ambient air temperature and airflow rates for converter DP8105 mounted horizontally with air flowing from input to output, mosfet temperature ? 120 c, vin = 12 v, vout = 5 v, and fsw= 500khz ambient temperature [c] 20 30 40 50 60 70 80 90 load current [adc] 0 1 2 3 4 5 6 500 lfm (2.5 m/s) 400 lfm (2.0 m/s) 300 lfm (1.5 m/s) 200 lfm (1.0 m/s) 100 lfm (0.5 m/s) 30 lfm (0.15 m/s) figure 2. available output current vs. ambient air temperature and airflow rates for converter DP8105 mounted horizontally with air flowing from input to output, mosfet temperature ? 120 c, vin = 12 v, vout = 5 v, and fsw= 1mhzw 6.2 efficiency curves 6.3 figure 5. efficiency vs input voltage at iout=5a, f sw=500khz figure 4. efficiency vs. output voltage, iout=5a, f sw=500khz figure 3. efficiency vs. load, vin=12v, fsw=500khz
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 10 of 35 6.4 power dissipation figure 6. efficiency vs load, vin=12v, fsw=1mhz figure 7. efficiency vs output voltage, iout=5a, fs w=1mhz figure 8. efficiency vs input voltage at iout=5a, f sw=1mhz figure 9. power dissipation vs vout, iout=5a, fsw=5 00khz figure 10. power dissipation vs vout, iout=5a, fsw= 1mhz
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 11 of 35 7. programmable features performance parameters of DP8105 dpol converters can be programmed via the industry standard i 2 c communication bus. each parameter has a default value stored in the volatile memory registers detailed in table 1. the setup registers 00h through 14h are programmed at the system power- up. when the user programs new performance parameters, they are stored in the dpm, which overwrites the values in the registers with the new data. upon removal of the input voltage, the defaul t values are restored. DP8105 converters can be programmed using the graphical user interface or directly via the i 2 c bus by using high and low level commands as described in the "dpm programming manual". table 1. DP8105 memory registers configuration registers name register address pc1 pc2 pc3 tc int don dof vlc cls dcl pc4 v1h v1l v2h v2l v3h v3l cp ci cd b1 protection configuration 1 protection configuration 2 protection configuration 3 tracking configuration interleave and frequency configuration turn-on delay turn-off delay voltage loop configuration current limit set-point duty cycle limit protection configuration 4 output voltage setpoint 1 (low byte) output voltage setpoint 1 (high byte) output voltage setpoint 2 (low byte) output voltage setpoint 2 (high byte) output voltage setpoint 3 (low byte) output voltage setpoint 3 (high byte) controller proportional coefficient controller integral coefficient controller derivative coefficient controller derivative roll-off coefficient 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 status registers name register address run st run enable / status status 0x15 0x16 monitoring registers name register address voh vol io tmp output voltage high byte (monitoring) output voltage low byte (monitoring) output current (monitoring) temperature (monitoring) 0x17 0x27 0x18 0x19 DP8105 parameters can be reprogrammed at any time during the system operation and service except for the digital filter coefficients, the switching frequency and the duty cycle limit, that can only b e changed when the dpol output is turned off. 7.1 output voltage the output voltage can be programmed in the gui output configuration window shown in figure 11 or directly via the i 2 c bus by writing into the vos register shown in figure 12. figure 11. output configuration window note that the gui shows the effect of setting pg, o v and uv limits as both values and graphical limit ba rs. vertical hashed lines are error bars for the overcurrent (oc) limit. 1.1.1 output voltage set-point the output voltage programming range is from 0.7 v to 5.5 v. the resolution is constant across the ran ge and is 2.5 mv. a total of 3 registers are provided : one should be used for the normal setpoint voltage; the other two can be used to define a low/high margining voltage setpoint. note that each register is 16bit wide and that the high byte needs always to b e written / read first. the writing of the low byte t riggers the refresh of the whole 16bit register (the high b yte is written to a shadow register). unlike other configuration registers, the dpol controller's vos registers are dynamic. changes to vos values can be made while the output is enabled over the i2c bus through register bypass commands and the dpol will change its output immediately.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 12 of 35 vos: output voltage set - point address: 0x0b 0x10 coefficient addr bits default v1h first vo setpoint high byte 0x0 b 8 v1l first vo setpoint low byte 0x0c 8 v2h second vo setpoint high byte 0x0d 8 v2l second vo setpoint low byte 0x0e 8 v3h third vo setpoint high byte 0x0f 8 v3l third vo setpoint low byte 0x10 8 mapping: - 12 bit data word, left aligned - 1lsb = 2.5mv note: - all registers are readable and writeable - always write and read the high byte first figure 12. output voltage set-point register vos 7.1.1 output voltage margining if the output voltage needs to be varied by a certa in percentage, the margining function can be utilized. the margining can be programmed in the dpol configuration window or directly via the i 2 c bus using high level commands as described in the ?dm7300 digital power manager programming manual?. 7.1.2 output load regulation control if the output voltage needs to be varied by a certa in percentage, the margining function can be utilized. the margining can be programmed in the dpol configuration window or directly via the i 2 c bus using high level commands as described in the ?dm7300 digital power manager programming manual?. in order to properly margin dpols that are connected in parallel, the dpols must be members of one of the parallel buses. refer to the gui system configuration figure 11 or directly via the i 2 c bus. in the DP8105 load regulation can be set to one of eight values: 0, 1.48, 2.95, 4.43, 5.9, 7.38 8.85, or 10.33 mv/a. upper regulation limit lower regulation limit light load v out i out vi curve without load regulation vi curve with load regulation heavy load headroom without load regulation operating point headroom with load regulation figure 13. optimal voltage positioning concept figure 14 shows a DP8105 dpol with 0 mv/a (load current) regulation. alternating high and low outpu t load currents causes large transients in vout to appear with each change. figure 14 transient response with regulation set to 0 mv/a. as the load regulation parameter is increased, step offsets in output voltage begin to appear, as shown in figure 15.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 13 of 35 figure 15 transient response with non-zero regulati on. the load regulation parameter is an important part of current sharing. it is used to set one dpol as a "master", by assigning a lower mv/a load regulation than all other dpols which share the load as "slaves". the dpol with the lowest regulation parameter sets the effective overall regulation. (s ee current sharing elsewhere in this document.) 7.2 sequencing and tracking turn-on delay, turn-off delay, and rising and falli ng output voltage slew rates can be programmed in the dpol configure sequencing window shown in figure 16 or directly via the i2c bus by writing in to the don, dof, and tc registers, respectively. the registers are shown in figure 17, figure 19, and figure 20. figure 16. dpol configure sequencing window 7.2.1 turn-on delay turn-on delay is defined as an interval from the application of the turn-on command until the output voltage starts ramping up. don7 don6 don5 don4 don2 don1 don0 bit 7 bit 0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bit 7:0 don[7:0] : turn-on delay time 00h: corresponds to 0ms delay after turn-on command has occurred ? ffh: corresponds to 255ms delay after turn-on comma nd has occurred don3 figure 17. turn-on delay register don 7.2.2 turn-off delay turn-off delay is defined as an interval from the application of the turn-off command until the outpu t voltage reaches zero (if the falling slew rate is programmed) or until both high side and low side switches are turned off (if the slew rate is not programmed). therefore, for the slew rate controlle d turn-off the ramp-down time is included in the turn -off delay as shown in figure 18. turn-off command internal ramp-down command v out user programmed turn-off delay, t df calculated delay t d time ramp-down time, t f ramp-down time, t falling slew rate dv f /dt figure 18. relationship between turn-off delay and falling slew rate as it can be seen from the figure, the internally calculated delay t d is determined by the equation below. dt dv v t t f out df d ? = , for proper operation t d shall be greater than zero. the appropriate value of the turn-off delay needs t o be programmed to satisfy the condition. if the falling slew rate control is not utilized, t he turn- off delay only determines an interval from the application of the turn-off command until both high side and low side switches are turned off. in this case, the output voltage ramp-down process is determined by load parameters.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 14 of 35 dof: turn - off delay configuration address: 0x06 u u r/w - 0 r/w - 0 r/w - 1 r /w - 0 r/w - 1 r/w - 1 --- --- dof5 dof4 dof3 dof2 dof1 dof0 bit 7 bit 0 bit 7:6 unimplemented: read as 0 bit 5:0 dof[5:0] : turn - off delay in ms 0x00 = 0ms 0x01 = 1ms 0x0b = 11ms (default) 0x3f = 63ms figure 19. turn-off delay register dof 7.3 turn-on characteristics once delays are accounted for, turn-on and turn-off characteristics are simply a function of slew rates , which are selectable. 7.3.1 rising and falling slew rates output voltage ramp up (and down) control is accomplished by programming the rising and falling slew rates of the output voltage, supported in the gui as shown in figure 16, which is implemented by the dpm through writing data to the tc register, figure 20. to achieve programmed slew rates, the output voltage is being changed in 10mv steps where duration of each step determines the slew rate. for example, ramping up a 1.0v output with a slew rate of 0.5v/ms will require 100 steps duration of 20 s each. duration of each voltage step is calculated by dividing the master clock frequency generated by th e dpm. since all dpols in the system are synchronized to the master clock, the matching of voltage slew rates of different outputs is very accurate as it can be seen in figure 21 and figure 26. during the turn on process, a dpol not only deliver s current required by the load (i load ), but also charges the load capacitance. the charging current can be determined from the equation below: dt dv c i r load chg = where, c load is load capacitance, dv r /dt is rising voltage slew rate, and i chg is charging current. tc: tracking configuration address: 0x03 u r/w - 0 r/w - 0 r/w - 1 r/w - 1 r/w - 1 r/w - 0 r/w - 0 --- r2 r1 r0 sc f2 f1 f0 bit 7 bit 0 bit 7 unimplemented : read as 0 bit 6:4 r[2:0] : vo rising slew rate 0 = 0.05 v/ms (default when in bus terminator mode) 1 = 0.1 v/ms (default) 2 = 0.2 v/ms 3 = 0.25 v/ms 4 = 0.5 v/ms 5 = 1.0 v/ms 6 = 2.0 v/ms 7 = reserved bit 3 sc : turn - off slew rate control 0 = disabled 1 = enabled (default) bit 2:0 f[2:0] : vo falling slew rate 0 = -0.05 v/ms 1 = -0.1 v/ms 2 = -0.2 v/ms 3 = -0.25 v/ms (default when in bus terminator mode ) 4 = -0.5 v/ms (default) 5 = -1.0 v/ms 6 = -2.0 v/ms 7 = reserved figure 20. tracking configuration register tc when selecting the rising slew rate, a user needs t o ensure that ocp chg load i i i < + where i ocp is the overcurrent protection threshold of the dpol. if the condition is not met, then the overcurrent protection will be triggered during the turn-on process. to avoid this, dv r /dt and the overcurrent protection threshold should be programmed to meet the condition above. 7.3.2 delay and slew rate combination the effect of setting slew rates and turn on/off de lays is illustrated in the following sets of figures.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 15 of 35 figure 21. tracking turn-on. rising slew rate is programmed at 0.5v/ms for each output. figure 22. turn-on with different rising slew rates . rising slew rates are v1-1v/ms, v2-0.5v/ms, v3-0.2v /ms. figure 23. sequenced turn-on. rising slew rate is programmed at 1v/ms. v2 delay is 2ms, v3 delay is 4 ms. figure 24 two outputs delayed 5ms. all slew rates a t 0.5v/ms. 7.3.2.1 pre-bias in some applications, power may "leak" from a powered circuit to an unpowered bus, typically through esd protection diodes. the dpwer ? controller in the DP8105 holds off turn on its outp ut until the desired ramp up point crosses the pre-bia s point, as seen in figure 25. figure 25. turn on into prebiased load. v3 is prebi ased by v2 via a diode. this figure was captured with an actual system where a diode was added to pre-bias a 1.5v bus from a 1.85v bus in order to simulate the effect of current leakage through protection circuits of unpowered logic connected to powered logic outputs (a common source of pre-bias in power systems).
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 16 of 35 1.1 turn-off characteristics turn of captures show that combining turn off delay s and ramp rates. note that while turnoff delays have a lower upper time limit as compared to turn on delay s, all ramp down rates are available independently to turn on and off. figure 26. tracking turn-off. falling slew rate is programmed at 0.5v/ms. figure 27. turn-off with tracking and sequencing. f alling slew rate is programmed at 0.5v/ms. 7.4 faults errors and warnings all dpol series converters have a comprehensive set of programmable fault and error protection functions that can be classified into three groups based on their effect on system operation: warnings , faults, and errors. these are warnings , errors and faults . warnings include thermal (overtemperature limit near) and power good (a warning in a negative sense.) faults in dp8000 dpols include overcurrent protection, overvoltage, overtemperature and tracking failure detection. errors include only undervoltage. control of responses to faults and errors are distributed between different dpol registers and are configurable in the gui. thresholds of overcurrent, over- and undervoltage detection, and power good limits can be programmed in the gui output configuration window (figure 11) or directly via the i 2 c bus by writing into the pc2 registers shown in figure 28. figure 28. protection configuration register pc2 note that the overvoltage and undervoltage protection thresholds and power good limits are defined as percentages of the output voltage. therefore, the absolute levels of the thresholds change when the output voltage setpoint is changed either by output voltage adjustment or by margining . overcurrent limits are set either in the gui dpol output configuration dialog or in the dpol's cls register as shown figure 29 note that the cls register includes bits which cont rol the regulation option settings. when writing into t his register be careful to not change regulation by accident. pc2: protection configuration register 2 1) address: 0x01 u u r/w - 0 r/w - 0 r/w - 1 r/w - 0 r/w - 0 r/w - 0 -- - --- pghl pgll ovpl1 ovpl0 uvpl1 uvpl0 bit 7 bit 0 bit7:6 unimplemented : read as 0 bit 5 pgh l : power good high level 1 = 105% of vo 0 = 110% of vo (default) bit 4 pgll : power good low level 1 = 95% of vo 0 = 90% of vo (default) bit 3:2 ovp l : over voltage protection level 00 = 110% of vo 01 = 120% of vo 10 = 130% of vo (default) 11 = 130% of vo bit 1:0 uvpl : under voltage protection level 00 = 75% of vo (default) 01 = 80% of vo 10 = 85% of vo 11 = 90% of vo 1) this register can only be wri tten when pwm is not active (run[run] is 0)
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 17 of 35 figure 29. current limit setpoint register cls 7.4.1 warnings this group includes overtemperature warning and power good signal. warnings do not turn off dpols but rather generate signals that can be transmitted to a host controller via the i 2 c bus. 7.4.1.1 overtemperature warning the overtemperature warning is generated when temperature of the controller exceeds 120c. the overtemperature warning changes the tw bit of the status register st. when the temperature falls belo w 117c, the pt bit is cleared and the overtemperature warning is removed. 7.4.1.2 power good power good (pg) is an open collector output that is pulled low, if the output voltage is outside of the power good window. the window is formed by the power good high threshold that is programmable at 105 or 110% of the output voltage and the power good low threshold that can be programmed at 90 or 95% of the output voltage. power good protection is only enabled after the output voltage reaches its steady state level. a programmable delay can be set between 0 and 150ms to delay the release of the pg pin after the voltage has reached the steady state level (see figure 16). this allows using the pg pin to reset l oad circuits properly. the power good protection remains active during margining voltage transitions . the threshold will vary proportionally to the volta ge change (see figure 30). the power good warning pulls the pg pin low and changes the pg bit of the status register st to 0. when the output voltage returns within the power good window, the pg pin is released high, the pg bit is cleared and the power good warning is removed. the power good pin can also be pulled low by an external circuit to initiate the power go od warning. at turn-off the pg pin can be programmed to either be pulled low immediately following the turn-off command, or then when the voltage actually starts t o ramp down (reset vs. power good functionality in figure 16). note : to retrieve status information, status monitoring in the gui dpm configure devices window should be enabled (ref er to digital power manager data sheet). the dpm will ret rieve the status information from each dpol on a continuo us basis. 7.4.2 faults this group includes overcurrent, overtemperature, undervoltage, and tracking protections. triggering any protection in this group will turn off the dpol . 7.4.2.1 overcurrent protection overcurrent protection is active whenever the outpu t voltage of the dpol exceeds the prebias voltage (if any). when the output current reaches the oc threshold, the pol control chip asserts an oc fault . the dpol sets the oc bit in the register st to 0. both high side and low side switches of the dpol are turned off instantly (fast turn-off). current sensing is across the dpols choke. to compensate for copper winding t c, compensation is added to keep the oc threshold approximately constant at temperatures above room temperature. note that the temperature compensation can be disabled in the dpol configure output window or directly via the i 2 c by writing into the cls register. however, it is recommended to keep the temperature compensation enabled. cls: current limit setting address: 0x08 r/w - 0 r/w - 0 r/w - 0 r/w - 1 r/w - 1 r/w - 0 r/w - 1 r/w - 1 lr2 lr1 lr0 tce cl 3 cl 2 cl 1 cl 0 bit 7 bit 0 bit 7:5 lr[2:0] : load regulation setting 0 = 0 v/a/f (default) 1 = 0.39 v/a/f 2 = 0.78 v/a/f 3 = 1.18 v/a/f 4 = 1.57 v/a/f 5 = 1.96 v/a/f 6 = 2.35 v/a/f 7 = 2.75 v/a/f bit 4 tce : temperature compensation for current limitation ena ble 0 = disabled 1 = enabled (default) bit 3:0 cls[3:0] : current limit set - point when vo stationary or falling 0x0 = 37% 0x1 = 47% 0xb = 140% (default) values higher than 0xb are translated to 0xb (140%)
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 18 of 35 7.4.2.2 undervoltage protection the undervoltage protection is only active during steady state operation of the dpol to prevent nuisance tripping. if the output voltage decreases below the uv threshold and there is no oc fault, th e uv fault signal is generated, the dpol turns off, a nd the uv bit in the register st is changed to 0. the output voltage is ramped down according to sequencing and tracking settings (regular turn-off) . 7.4.2.3 overtemperature protection overtemperature protection is active whenever the dpol is powered up. if temperature of the controlle r exceeds 130c, the ot fault is generated, dpol turns off, and the ot bit in the register st is cha nged to 0. the output voltage is ramped down according to sequencing and tracking settings (regular turn-o ff). if non-latching otp is programmed, the dpol will restart as soon as the temperature of the controlle r decreases below the overtemperature warning threshold of 120c. 7.4.2.4 tracking protection ramp up and down operations are under control by the dpol. tracking protection, however, is active only when the output voltage is ramping up. the purpose of the protection is to ensure that the voltage differential between multiple rails being tracked does not exceed 250mv. this protection eliminates the need for external clamping diodes between different voltage rails which are frequentl y recommended by asic manufacturers. when the tracking protection is enabled, the dpol continuously compares actual value of the output voltage to its programmed value as defined by the output voltage and its rising slew rate. if absolut e value of the difference exceeds 250mv, the tracking fault signal is generated, the dpol turns off, and the tr bit in the register st is changed to 0. both hig h side and low side switches of the dpol are turned off instantly (fast turn-off). the tracking protection can be disabled, if it contradicts requirements of a particular system (fo r example turning into high capacitive load where rising slew rate is not important). it can be disab led in the dpol configure fault window or directly via the i 2 c bus by writing into the pc1 register. 1.1.1 faults and margining as noted earlier, uv and ov protection settings are a percentage of vout. as vout ramps between nominal, low or high margin values, uvp and ovp limits adjust accordingly. this is illustrated in f igure 30. the middle plot of vo (vout) level is the resul t of a low margining command. note that tracking is not re-enabled during changes to vout from margining commands. it shuts off when pg is asserted. ovp limit pg high limit uvp limit vo time vo pglow limit t r k _ h t r k _ l vo_rise vo_stable vo_fall vo_stable vo_rise vo_stable vo_fall ovp limit pg high limit uvp limit pglow limit pglow limit uvp limit ovp limit pg high limit 1.0v run oc enabled pre-biased output pg enabled figure 30. protection enable conditions
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 19 of 35 7.4.3 errors this protection group includes only overvoltage protection. 7.4.3.1 overvoltage protection the overvoltage protection is active whenever the output voltage of the dpol exceeds the pre-bias voltage (if any). if the output voltage exceeds the overvoltage protection threshold, the overvoltage error signal is generated, the dpol turns off, and the ov bit in the register st is changed to 0. the high side switch is turned off instantly, and simultaneo usly the low side switch is turned on to ensure reliable protection of sensitive loads. the low side switch provides low impedance path to quickly dissipate energy stored in the output filter and achieve effective voltage limitation. the ov threshold can be programmed from 110% to 130% of the output voltage setpoint, but not lower than 0.5v. also the ov threshold will always be at least 0.25v above th e setpoint. 7.4.4 fault and error latching the user has the option of setting up any protectio n option as either latching/non-latching and propagating or non-propagating. propagation and latching for each dpol is set in th e gui (figure 31 below) or directly via the i 2 c by writing into the pc1 register shown in figure 32. figure 31. gui dpol fault latching and propagation option window if the non-latching protection is selected, a dpol will attempt to restart every 130ms until the condition that triggered the protection is removed. when restarting, the output voltages follow tracking and sequencing settings. if the latching type is selected, a dpol will turn off and stay off. the dpol can be turned on after 130ms, if the condition that caused the fault is removed and the respective bit in the st register was cleared, or the turn on command was recycled, or the input voltage was recycled. pc1: protection configuration register 1 address: 0x00 r/w - 0 r/w - 1 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 1 r/w - 1 tre pve trc otc occ uvc ovc pvc bit 7 bit 0 bit 7 tre : tracking fault enable 1 = enabled 0 = disabled bit 6 pve : phase voltage error enable 1 = enabled 0 = disabled bit 5 tr c : tracking fault protection configuration 1 = latching 0 = non-latching bit 4 otc : over temperature protection configuration 1 = latching 0 = non-latching bit 3 occ : over current protection configuration 1 = latching 0 = non- latching bit 2 uvc : under voltage protection configuration 1 = latching 0 = non- latching bit 1 ovc : over voltage protection configuration 1 = latching 0 = non- latching bit 0 pvc : phase voltage protection configuration 1 = latching 0 = non- latching
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 20 of 35 figure 32. protection configuration register pc1 7.4.5 fault and error turn off control in the gui dpol fault dialog is a column of spin controls which set the turn-off style ot, uv and ov events. the choices are defined as: sequenced : outputs shut down according to ramp down rate control settings. critical : both high side and low side switches of the dpol are turned off instantly emergency : the high side switch is turned off instantly, and simultaneously the low side switch i s turned on to ensure reliable protection of sensitiv e loads 7.4.6 fault and error status status of dpol protection logic is stored in the dpol's st register shown in figure 33. when status monitoring is enabled for a group, the dpm will read this register and make the information available for uses such as gui monitor display. figure 33. protection status register st 7.4.7 fault and error propagation the feature adds flexibility to the fault managemen t scheme by giving users control over propagation of fault signals within and outside of the system. the propagation means that a fault in one dpol can be programmed to turn off other dpols and devices in the system, even if they are not directly affected by the fault 1.1.1.1 fault propagation when propagation is enabled, the faulty dpol pulls its ok pin low. this signals to the dpm and any other dpol connected to that signal, that the dpol has a fault or error condition. a low ok line initi ates turn-off of other dpols connected to the same ok line with the same turn-off behavior as the faulty dpol. the turn-off type is encoded into the ok line when it transitions from high to low. pc1: protection configuration register 1 address: 0x00 r/w - 0 r/w - 1 r/w - 0 r/w - 0 r/w - 0 r/w - 0 r/w - 1 r/w - 1 tre pve trc otc occ uvc ovc pvc bit 7 bit 0 bit 7 tre : tracking fault enable 1 = enabled 0 = disabled bit 6 pve : phase voltage error enable 1 = enabled 0 = disabled bit 5 tr c : tracking fault protection configuration 1 = latching 0 = non-latching bit 4 otc : over temperature protection configuration 1 = latching 0 = non-latching bit 3 occ : over current protection configuration 1 = latching 0 = non- latching bit 2 uvc : under voltage protection configuration 1 = latching 0 = non- latching bit 1 ovc : over voltage protection configuration 1 = latching 0 = non- latching bit 0 pvc : phase voltage protection configuration 1 = latching 0 = non- latching st: status register address: 0x16 r - 1 r - 0 r /w - 1 1) r /w - 1 1) r /w - 1 1) r /w - 1 1) r /w - 1 1) r /w - 1 1) tw pg tr ot oc uv ov pv bit 7 bit 0 bit 7 t w : temperature warning bit 6 pg : power good warning (high and low) bit 5 tr : tracking fault bit 4 ot : over temperature fault bit 3 oc : over current fault bit 2 uv : under voltage fault bit 1 ov : over voltage error bit 0 pv : reserve d note: an activated fault is encoded as 0 1) writing a 1 into a fault/error bit clears a latching fault/error st: status register address: 0x16 r - 1 r - 0 r /w - 1 1) r /w - 1 1) r /w - 1 1) r /w - 1 1) r /w - 1 1) r /w - 1 1) tw pg tr ot oc uv ov pv bit 7 bit 0 bit 7 t w : temperature warning bit 6 pg : power good warning (high and low) bit 5 tr : tracking fault bit 4 ot : over temperature fault bit 3 oc : over current fault bit 2 uv : under voltage fault bit 1 ov : over voltage error bit 0 pv : reserve d note: an activated fault is encoded as 0 1) writing a 1 into a fault/error bit clears a latching fault/error
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 21 of 35 1.1.1.2 grouping of dpols dpwer ? dpols can be arranged in groups of up to 4, 8, 16 or 32 dpols (depending upon the dpm model used). membership in a group is set in the gui in the dpm / configure / devices dialog, and implemented in hardware by connecting the ok pins of each dpol in the group to the matching ok input on the dpm. in order for a particular fault or error to propaga te through the ok line, propagation needs to be checked in the gui dpol configure / fault management window figure 34. figure 34. dpm configure faults window note that the turn-off type of the fault as it propagates through the dpm will remain unchanged. propagation options for dpols can be read or set in the dpol pc3 register shown in figure 35. figure 35. protection configuration register pc3 7.4.7.1 front end and crowbar if an error is propagated to at least the group lev el, the dpm can also be configured to generate commands to turn off a front end (a dc-dc converter generating the intermediate bus voltage) and to trigger an optional crowbar protection to accelerate removal of the ibv voltage. 7.4.7.2 propagation process understanding fault and error propagation is easier with the following examples. the first example is of of non-propagation from a dpol, as shown in figure 36. an undervoltage error shuts down the vo, but since propagation was not enabled, ok-a is not pulled down and vo2 stays up. pc3: protection configuration regis ter 3 address: 0x02 u u r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 r/w - 1 --- --- trp otp ocp uvp ovp pvp bit 7 bit 0 bit 7:6 unimplemented : read as 0 bit 5 trp : tracking protection propagation 0 = disabled 1 = enabled bit 4 otp : over temperature prote ction propagation 0 = disabled 1 = enabled bit 3 ocp : over current protection propagation 0 = disabled 1 = enabled bit 2 uvp : under voltage protection propagation 0 = disabled 1 = enabled bit 1 ovp : over voltage protection propagation 0 = disabled 1 = enabled bit 0 pvp : reserved
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 22 of 35 figure 36. no group fault propagation figure 37 shows a scope capture an actual system when undervoltage error detection is set to not propagate. in this example, the dpol connected to scope ch 1 encounters the undervoltage fault after turn-on. because fault propagation is not enabled for this dpol, it alone turns off and generates the uv fault signal. because a uv fault triggers the sequenced turn-off, the dpol meets its turn-off delay and fal ling slew rate settings during the turn-off process as shown in the trace for ch1. since the uv fault is programmed to be non-latching, the dpol will attempt to restart every 130 ms, repeating the process described above until the condition causing the undervoltage is removed. the 130ms hiccup interval is guaranteed regardless of the turn-off d elay setting. figure 37. turn-on into uvp on v3. the uv fault is programmed to be non-latching. ch1 ? vo1, ch2 ? vo2(group a), ch3 ? vo3 (group b) vo4 not shown. the next example is intra-group propagation, the dpol propagates its fault or error events. here fau lt propagation between dpols is enabled. in figure 38 the dpol powering output vo1 again encounters an undervoltage error. it pulls its ok l ine low. since the dpol powering output vo2 (ch3 in the picture) belongs to the same group (a in this case), pulling down ok-a tells that dpol to execute a regular turn-off. figure 38. intra group fault propagation since both vo1 and vo2 have the same delay and slew rate settings they will continue to turn off a nd on synchronously every 130ms as shown in figure 39 until the condition causing the undervoltage is removed.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 23 of 35 note that the dpol powering the output vo2 (ch3) actually reaches its voltage set point before the e rror in vo1 is detected. figure 39. turn-on into uvp on v3. the uv fault is programmed to be non-latching and propagate from group c to group a. ch1 ? v3 (group c), ch2 ? v2, ch3 ? v1 (group a) the turn-off type of a dpol fault/error as propagat ed by the faulty dpol via the ok line is propagated through the dpm to other dpols connected to other groups (per configuration in ) through its connecti on to their ok line or lines. this behavior assures that all dpols configured to be affected through group linkages will switch off with the same turn-off type. a summary of protection support, their parameters and features are shown in table 2. table 2. summary of protection parameters and featu res code name type when active turn off low side switch propagation disable tw temperature warning warning whenever v in is applied no n/a status bit no pg power good warning during steady state no n/a pg no tr tracking fault during ramp up fast off critical yes ot overtemperature fault whenever v in is applied regular off sequenced or critical no oc overcurrent fault when v out exceeds prebias fast off critical no uv undervoltage fault during steady state regular o ff sequenced or critical no ov overvoltage error when v out exceeds prebias fast on critical or emergency no
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 24 of 35 1.2 ok fault and error coding dpwer ? dpols have an additional functionality added to th e ok line signal. the ok line is used to propagate and receive information from other devices in the p ower system belonging to the same group as to the k ind of turn- off procedure a device has initiated because of a f ault. figure 40 shows the three types of ok encoding. the bubbles show when the sd and ok line logic levels are sampled by dpol and the dpm logic. figure 40. ok severity encoding waveforms note that the ok line state changes are always exec uted by dpols at the negative edge of the sd line. the chart shows shut down response types as the use r can select the kind of response desired for each type of fault or error (within the limits of choice provide d for each type of fault or error) .all dpol device s in the same group are expected to trigger the same turn-off pro cedure in order to maintain overall tracking of out put voltages in the system. and when fault propagation is set to go from one group to another, the encoding is pass ed along un-changed. 7.5 switching and compensation dpwer ? dpols utilize the digital pwm controller. the controller enables users to program most of the pwm performance parameters, such as switching frequency, interleave, duty cycle, and feedback loo p compensation. 7.5.1 switching frequency the switching frequency of the DP8105 can be programmed to either 500khz or 1mhz in the gui pwm controller window shown in figure 41 or directly via the i2c bus by writing into the int register shown in figure 42. note that the content of the register can be changed only when the dpol is turned off. each dpol is equipped with a pll that locks to the 500 khzsd signal which is generated by the dpm. this sets up for switching actions to be synchronou s to the falling edge of sd by all dpols, which are thereby kept coordinated to each other. although synchronized to sd, switching frequency selection is independent for each dpol, with the exception of shared load bus groups, where dpols attached to a shared load bus are forced to use the same frequency by the gui. figure 41. pwm controller window in some applications, switching at higher frequenci es is desirable even though efficiency is lower, becau se it allows for better transient response or lower application system noise.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 25 of 35 7.5.2 interleave interleave is defined as a phase delay between the synchronizing slope of the master clock on the sd pin and pwm signal of a dpol. the interleave can be programmed in the dpol controller configure compensation window or directly via the i 2 c bus by writing into the int register. int: interleave configuration address: 0x04 r r r/w - 0 u r/w - 0 r/w - 0 r/w - 0 r/w - 0 phs1 phs0 frq --- int3 int2 int1 int0 bit 7 bit 0 bit 7:6 phs[1:0] : phase selection 0 = single phase (pwm0) 1 = dual phase (pwm0 and pwm2) 2 = triple phase (pwm0, pwm1 and pwm2) 3 = quad phase (pwm0, pwm1, pwm2 and pmw3) bit 5 frq : pwm frequency selection 0 = 500 khz (default) 1 = 1000 khz bit 4 unimplemented : read as 0 bit 3 :0 int[3 :0] : pwm interleave phase with respect to sd line 0x00 = 0 phase lag 0x01 = 22.5 phase lag 0x02 = 45 phase lag 0x1f = 337.5 phase lag figure 42. interleave configuration register int 7.5.3 interleave andf input bus noise when a dpol turns on its high side switch there is an inrush of current. if no interleave is programme d, inrush current spikes from all dpols in the system reflect back into the input source at the same time , adding together as shown in figure 43. figure 43. input voltage noise, no interleave figure 44 shows the input voltage noise of the thre e- output system with programmed interleave. instead of all three dpols switching at the same time as in the previous example, the switching cycle of dpols v1, v2, and v3 start at 67.5, 180, and 303.75 of phase delay, respectively. noise is spread evenly across the switching cycle resulting in more than 1 .5 times reduction. figure 44. input voltage noise with interleave 7.5.4 interleave and current sharing noise similar noise reduction can be achieved on the output of dpols connected in parallel. figure 45 an d figure 46 show the output noise of two dpols connected in parallel without and with a 180 interleave, respectively. resulting noise reduction is more than 2 times and is equivalent to doubling switching frequency or adding extra capacitance on the output of the dpols.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 26 of 35 figure 45. output voltage noise, full load, no inte rleave figure 46. output voltage noise, full load, 180 interleave 7.5.5 duty cycle limit the DP8105 is a step-down converter therefore v out is always less than v in . the relationship between the two parameters is characterized by the duty cycle and can be estimated from the following equation: min in out v v dc . = , where, dc is the duty cycle, v out is the required maximum output voltage (including margining), v in.min is the minimum input voltage. the dpol controller sets pwm duty cycle higher or lower than the above to compensate for drive train losses or to pull excess charge out of the output f ilter to keep the output voltage where it is supposed to be. a side effect of pwm duty cycle is it also sets the rate of change of current into the output filter. a high limit helps deal with transients. however, if this is too high, an overcurrent alarm can be tripped. thus dc limiting must be a compromise between supplying drive train losses and avoiding nuisance trips from transient load responses. the duty cycle limit can be programmed in the gui pwm controller window figure 41 or directly via the i 2 c bus by writing into the dcl register shown in figure 47. the gui will supply its own estimate of the best dc limit if the propose button is clicked. d cl: duty cycle limitation address: 0x09 r/w - 1 r/w - 1 r/w - 1 r/w - 0 r/w - 1 r/w - 0 u u dcl5 dcl4 dcl3 d cl2 dcl1 dcl0 --- --- bit 7 bit 0 bit 7: 2 dcl[5:0] : duty cycle limitation 0x00 = 0 0x01 = 1/64 0x02 = 2/64 0x1f = 63/64 bit 1 :0 unimplemented : read as 0 figure 47. duty cycle limit register 7.6 feedback loop compensation programming feedback loop compensation allows optimizing dpol performance for various application conditions. for example, increase in bandwidth can significantly improve dynamic response. the dpol implements a programmable pid (proportional, integral, and derivative) digital controller to shape the open loop transfer function for desired bandwidth and phase/gain margin. feedback loop compensation can be programmed in the gui pwm controller window by setting kr (proportional), ti (integral), td (derivative), and tv (derivative roll-off) parameters or directly writin g into the respective registers (cp, ci, cd, b1). note tha t the coefficient kr and the timing parameters (ti, t d, tv) displayed in the gui do not map directly to the register values. it is therefore strongly recommend ed to use only the gui to set the compensation values. the gui offers 3 ways to compensate the feedback loop: auto-compensation : the gui will calculate compensation settings from either information entered as to output capacitors in the application
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 27 of 35 circuit, or, if the sysid function has been run, th e frequency response measured through the sysid function in the target dpol. this method is usually sufficient, but is sensitive to accurate accounting of capacitor values and esr. the gui displays the results of running auto-compensation as a set of graphs and compensation values. manual compensation : the gui supports manually adjusting feedback compensation parameters. as the parameters are changed the gui recalculates expected frequency and phase performance. system identification (sysid) and auto- compensation : hardware built into the dpol controller that injects pseudo random noise into th e pwm stream and observes the response of the output voltage. the gui collects this data and calculates actual system frequency response. this allows the auto-compensation function to have a better idea of actual output filter characteristics when it calculates feedback coefficients. using noise to plumb the output filter requires cur rent values for compensation be good enough that injected signal can be extracted from system noise and the added noise does not trip a fault or error response. a moderately workable solution for compensation must be obtained by calculating from assumed system component values before invoking sysid. 7.7 transient response the following figures show the deviation of the output voltage in response to alternating 25 and 75 % step loads applied at 2.5a/ s. the dpol converter is switching at 500khz and has 10 x 22 f ceramic capacitors connected across the output pins. bandwidth of the feedback loop was optimized for slightly overdamped response. increasing the load regulation parameter induces a droop, or offset, in the output at the higher curre nt load. figure 48. transient response with regulation set t o 0.0 mv/a. as noted earlier, increasing the load regulation parameter provides load dependant dynamic load positioning. this shows up in figure 49 figure 49. transient response with regulation set t o 6.53 mv/a 7.8 load current sharing DP8105 dpwer ? dpol converters are not equipped for current sharing.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 28 of 35 7.9 monitoring along with status information, dpol converters can monitor their own performance parameters such as output voltage, output current, and temperature. the output voltage is measured at the output sense pins, output current is measured using the esr of the output inductor and temperature is measured by the thermal sensor built into the controller ic. ou tput current readings are adjusted based on temperature readings to compensate for the change of esr of the inductor with temperature. a 12-bit analog to digital converter (adc) converts the output voltage, output current, and temperature into a digital signal to be transmitted via the ser ial interface (12bits for the voltage, 8 bits for the current and temperature). monitored parameters are stored in registers (vom, iom, and tmon) that are continuously updated in the dpm at a fixed refresh rate of 1sec. these monitoring values can be accessed via the i 2 c interface with high and low level commands as described in the ??dpm programming manual?. figure 50 is a capture of the gui system monitor while operating the zm7300 evaluation board. 1.2.1 in system monitoring in system parametric and status monitoring is implemented through the i2c interface. the appropriate protocols are covered in the zm7300 dpm programming manual. the gui uses the published commands. in writing software for i2c bus transactions, it is important to note that i2c responses are lower in priority in dpm operation than sd bus transactions. if an i2c transaction overlaps an sd bus transactio n, the dpm will put the i2c bus on "hold" until it completes its sd activity. the gui is aware of this and such delays are transparent. when directly polling dpols for information, settin g i2c bus timeouts too low can cause hangups where the dpm is waiting for the i2c master to complete a transaction and the master has timed out. to avoid such timeout related problems, set i2c interface timeout to greater than the time required for polli ng all dpols, or 150ms (whichever is greater). see the programming manual referenced above for the equation used to calculated worst case polling duration. figure 50. dpm monitoring window
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 29 of 35 8. adding dpols into the system dpol converters are added to a dpwer ? system through the dpm configuration/devices dialog. clicking on an empty address location brings up a menu which allows specifying which dpol type is needed. figure 51 below is an example of a typical dpwer ? system. note that auto-on, p-monitor and s-monitor options are only configurable by group, and not by individu al dpol configuration. these options affect only dpm behavior. enabling them does not burden a dpol. auto-on sets a group to turn on once all ibv power is available and dpols are configured. p-monitor enables periodic query of vout, iout and temp values from each dpol in the group where it is enabled (dpols will always measure these parameters in an ongoing basis even if vout is not enabled. s-monitor enables periodic query of dpol status. while a dpm will always be able to detect a low ok condition, it requires this option enabled for moni tor function to query status registers. figure 51 evaluation board configuration showing cu rrent share bus assignment
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 30 of 35 9. testing fault and error response included in the architecture of dpwer ? dpols is a mechanism for simulating errors and faults. this allows the designer to test their response configuration without actually needing to induce th e fault. the power-one gui supports this feature in the monitor window when monitoring is active (see figure 52). when monitoring is off, the fault injec tion control boxes are disabled and grayed out. figure 52. fault injection controls fault injection into a dpol requires selecting that dpol in the pol status dialog in the left column of the monitoring dialog window. as long as the checkbox is checked, the fault trigger is present i n the dpol. an injected fault is handle by the dpol i n the same fashion as an actual fault. it therefore g ets propagated to the other dpols / groups and shuts down in the programmed way the dpol/group/system as programmed for that fault.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 31 of 35 figure 53. example of overtemp fault injection in t he gui in we see the effects of injecting an overtemp (ot) fault. note that dpol-0 shows an ot fault. dpol-0 and -1 are in the same group and fault propagation for the dpo l is to propagate to the group. dpol -4 and above a re in groups b and c. propagation is not enabled from gro up a to b. the ot fault shows up as an orange indicator in the dpol and run status leds. group leds show yellow, indicating all of the members of the group have shu t down. fault recovery depends whether the fault is a latch ing or non-latching fault: a non latching fault is cleared by unchecking the c heckbox (clears the fault trigger). the dpol will r e-start after the 130ms time out of non-latching faults (hiccup time) (group and system follows restart). latching faults clear in one of two ways. the first method is to clear the fault trigger (uncheck the checkbox) (note: the dpol remains off since the fault is latching). alternately, a latched fault can be cleared by togg ling the en pin or by commanding the dpol to turn-o ff and turn- off again via the gui interface (obviously more con venient). therefore, once the fault trigger is clea red, click the ?off? button of the dpol or group (clears the fault , status leds turn back to green) and then the ?on? button of the dpol or group to re-enable it.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 32 of 35 10. application shown in figure 54s a block diagram of a multiple d pol power system. the key interconnections needed between the dpm and the dpols are intermediate volt age bus (ibv), sd, ok (a - c), and, between the fir st two dpols which share a bus load, their cs connections. each dpol has its own output bulk filter capacitor s. this illustrates how simple a dpol based system is to im plement in hardware. sd provides synchronization of all dpols as well as communication. pg, not shown, is o ptional, though this is usually used with auxiliary power supplies that are not digitally controlled. figure 54. multi-dpol power system diagram shown in figure 55 is a more detailed schematic of a typical application using a dm7300 series digital power manager (dpm) and at least one DP8105 point-of-load converter (dpol). additional dpwer ? series dpols may be connected (note sd and ok dashed lines "to other dpols"). as noted earlier, ok connections are determined by which group a given dpol is assigned to in the user's application. in this case the DP8105 is connected to ok-a. shown connected to the DP8105 ok pin is an optional low value resistor helpful in some cases for fault isolation. the type, value, and the number of output capacitor s shown in the schematic are required to meet the specifications published in the data sheet. howeve r, all dpwer ? dpols are fully operational with different configurations of output capacitors. the supervisor y reset circuit in the above diagram, u2, is recomm ended for systems where the 3.3v supply to the dpm does not t urn on faster than 0.5 v/ms. the dpm does require some passive components which are located close to that part but not shown in the diagram above. note: the DP8105 is footprint compatible with the z y8105?no change in pcb is needed to upgrade to dpwe r ? parts. however, configuration data must be altered through the power-one i2c gui and programmed into t he dpm. when upgrading to dpwer ? , mixing zy and dp series devices is not recommended. all parts must be upgraded .
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 33 of 35 figure 55. typical application with digital power m anager and i 2 c interface notes:
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 34 of 35 11. safety the DP8105 dpol converters do not provide isolation from input to output. the input devices powering DP8105 must provide relevant isolation requirements according to all iec60950 based standards. nevertheless, if the system using the converter needs to receive safety agency approval, certain rules must be followed in the design of the system. in particular, all of the creepage and clearance requirements of the end-use safety requirements must be observed. these requirements are included in ul60950 - csa60950-00 and en60950, although specific applications may have other or additional requirements. the DP8105 dpol converters have no internal fuse. if required, the external fuse needs to be provided to protect the converter from catastrophic failure. re fer to the ?input fuse selection for dc/dc converters? application note on www.power-one.com for proper selection of the input fuse. both input traces and the chassis ground trace (if applicable) must be capabl e of conducting a current of 1.5 times the value of t he fuse without opening. the fuse must not be placed i n the grounded input line. abnormal and component failure tests were conducted with the dpol input protected by a fast- acting 65 v, 15 a, fuse. if a fuse rated greater th an 15 a is used, additional testing may be required. in order for the output of the DP8105 dpol converter to be considered as selv (safety extra low voltage), according to all iec60950 based standards, the input to the dpol needs to be supplied by an isolated secondary source providing a selv also.
DP8105 5a dc-dc intelligent dpol data sheet 8v to 14v input ? ?? ? 0.7v to 5.5v output bcd.00261 rev. 1.0, 12 feb 2013 www.power-one.com page 35 of 35 12. mechanical drawings all dimensions are in mm tolerances: xx.x: 0.1 xx.xx: 0.05 figure 56. mechanical drawing figure 57. recommended footprint ? top view notes: 1. nuclear and medical applications - power-one pro ducts are not designed, intended for use in, or aut horized for use as critical components in life support systems, equipment used in hazardous environments, or nuclear control syste ms without the express written consent of the respective divisional president of p ower-one, inc. 2. technical revisions - the appearance of products , including safety agency certifications pictured o n labels, may change depending on the date manufactured. specifications are subject t o change without notice. i 2 c is a trademark of philips corporation.

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